This last semester was definitely a fight to complete despite taking only 3 classes. I pulled more all-nighters and EECS’d it more times than all of my past semesters combined. For all of my hard work, this was certainly one of my most interesting semesters. While I am sad to be graduating, especially after all of the time lost to COVID, it will be exciting to see what the next chapter of my life has in store. That next chapter will start in July where I’ll be a Tesla firmware engineer! I’ll be taking a well deserved vacation in the interlude.
CS152 – Computer Architecture and Engineering
While I didn’t go to a single lecture or discussion past the first few, this was an eye-opening class in learning how modern CPUs are designed and how they can be so performant. Topics ranging from out-of-order processors, register renaming, branch prediction, to cache coherence all ended up being conceptually pretty simple and not just magic. My favorite part was finally implementing a Spectre attack in simulation and having it work perfectly. The workload was quite light and relatively rewarding. Much like CS161, it’s a class that doesn’t consume much time and fits well into any schedule.
EE142 – Integrated Circuits for Communications
Much like its prerequisite EE105, this was easily one of the most difficult classes I’ve ever taken. The workload was manageable, but the material went over my head more times than not. Taking the class for a grade really did not help things. While the initial material on transmission lines, waves, noise, and distortion wasn’t terrible to pick up, once we got to amplifiers, mixers, and oscillators I was completely out of my element. I really should’ve taken EE140 prior. Still, I learned a good amount in this class. The labs were really fun and rewarding and the TAs were amazing. I can’t say much about the lectures and discussions since I didn’t go to a single one past the first few, but I’d wager they were solid too. Highly recommended if you’re into analog circuits but this was not the class for me.
EE194 – Advanced Topics in Circuit Design (22nm SoC for IoT)
Mostly due to its open-ended nature, this was one of the heaviest but most rewarding classes I’ve ever taken. Not for the faint of heart, this class really opened up my eyes to the wonders of chip design and just how much Berkeley has contributed to the field. The goal of the class is to take a team of ~20 undergraduate and graduate students and do a chip “tapeout”. Since our class had ~40 students, we split into two teams, one doing an ML accelerator chip and one doing a mixed signal chip. In what ended up being a perfect match, I was on the RF digital team for the mixed signal chip which was tasked with validating and updating the past BLE module and adding 802.15.4 support.
Since the previous team’s work was understandably rushed and poorly documented, I ended up teaching myself how the entire thing was designed and implemented. Since I hate MATLAB, I wrote Python simulations to design the DSP pathway and CDR and figure out just how low an SNR we could get away with. Transferring that design to RTL in Chisel was daunting at first but ended up being pretty straightforward. At the end of the day, I was quite proud of the work I did.
I had so much fun with Chisel that I decided to spend a couple of days not studying for the EE142 final and instead developing a workflow for deploying Chisel on FPGAs in MacOS. Since I’m graduating and won’t have VMware anymore, I figured out how to load Vivado in a Docker image and compile the Chisel-generated Verilog there. Check it out!
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